A large-scale integrated circuit (LSI) has an output buffer which outputs a plurality of signals to an external LSI or to other internal macros. For example, signals of a data bus with a plurality of bits are latched by a plurality of latch circuits such as flip-flops in response to a reference clock, and the latch circuit outputs are output via respective corresponding output buffers. When a plurality of signals simultaneously change from L level to H level, large currents flow in the power supply wiring of the plurality of output buffers, and power supply noise is generated. Conversely, when a plurality of signals simultaneously change from H level to L level, large currents flow in the ground wiring of the plurality of output buffers, and ground noise is generated. Such noise is called simultaneous switching noise (SSN), and becomes a large noise source when a plurality of output buffers with large driving capacity are switched simultaneously in the same direction.
Methods to suppress such simultaneous switching noise are described in Patent Documents Japanese Patent Application Laid-open No. 2007-129601, Japanese Patent Application Laid-open No. 2004-334271 and Japanese Patent Application Laid-open No. H9-181593. In all cases, an attempt is made to suppress simultaneous switching by adding a predetermined fixed delay to a plurality of signals and generating skew in the plurality of signals.
However, the output timing of a plurality of signals changes for various reasons, and in some cases it may not be possible to appropriately suppress noise due to simultaneous switching simply by adding the predetermined fixed delay.
For example, depending on the LSI operating environment, the LSI internal operating speed differs, and the timing of internal signals differs, so that using a method of inserting a fixed delay circuit for output signals, there are cases in which simultaneous switching noise cannot be appropriately reduced. Further, the AC specifications of external LSIs receiving output signals from an LSI, such as for example the input setup time, hold time and similar, differ depending on the LSI, and so there are cases in which the AC specifications cannot be satisfied by a method of inserting a fixed delay for output signals.